An EPROM (electrically programmable read-only memory) for use in reading only and having silicon gates known in the art is a NOR-type memory cell array shown for example in Japanese Patent Application Kokai Publication No. 40698/1987.
FIG. 2 shows a circuit diagram of a non-volatile memory device of this type. In the figure, 1 is a column decoder, 2 is a row decoder, 3 is a sense amplifier, T.sub.c0, T.sub.c1, . . . , T.sub.cn are column select transistors (hereinafter referred to as Y gates), Q.sub.00, Q.sub.01, . . . , Q.sub.mn are memory cells each comprised of a transistor. Transistors Q are arrayed in rows and columns. Y.sub.0 to Y.sub.n are Y gate select signals, X.sub.0 to X.sub.m are word lines for supplying the output signals of the row decoder 2 to the memory gates as select signals. A plurality of bit lines b.sub.0 . . . b.sub.n are shown in FIG. 2 orthogonal to the rows (word lines).
With the above non-volatile memory device, the column decoder circuit 1 activates one of the Y gate select signals Y.sub.0 to Y.sub.n thereby to actuate one of the column select transistors to couple the corresponding one of the bit lines b.sub.0 to b.sub.n, to sense amplifier 3. The row decoder 2 similarly selects one of the word lines X.sub.0 to X.sub.m. In this way, a memory cell at the intersection is selected and the sense amplifier converts the current of the memory cell into a voltage and amplifies it. Reading is thereby achieved.
However, with the above described prior art device, the source electrodes are connected to a common GND conductor, so that when one of the word lines X.sub.0 to X.sub.m is selected at the time of data reading, the electric charges of the unselected bit lines are discharged to the common GND conductor through the unselected memory cells connected to the selected word line, and the potentials on the unselected bit lines are brought to the GND potential. When the data in the memory cells are read by switching the Y gates, the bit lines which are at the GND potential must first be precharged, i.e. charged to a level near the sense potential of 1.3 V, before the sense current is detected. Thus, normal reading operation is not achieved immediately, and reading takes time.
In addition, with this configuration, the voltage amplitude which appears on the bit lines due to the on-resistance of the Y gate and the voltage drop due to the memory cell current retards the data reading. That is, the on-resistance of the Y gate is normally in the order of 1 k.OMEGA., and the current amplitude dependent on the data in the memory cell is 0 to 60 .mu.A, so a voltage of about 60 mV is impressed on the bit line. As the voltage amplitude becomes larger, the time taken for the charge and discharge of the parasitic capacitance is longer. As a result, the data reading is retarded. This problem may be seen to be solved if the on-resistance of the Y gate is reduced. However, with a lower on-resistance of the Y gate, the load for the column decoder is heavier, and the rise time and the fall time of the column decoder output are longer, and the operation is not speedy.